Using GPCE principles for hardware systems and accelerators: (bridging the gap to HW design)

Abstract

Moore's Law has precipitated a crisis in the creation of hardware systems (ASICs and FPGAs)-how to design such enormously complex concurrent systems quickly, reliably and affordably? At the same time, portable devices, the energy crisis, and high performance computing present a related challenge-how to move complex and high-performance algorithms from software into hardware (for more speed and/or energy efficiency)?