Refining Real-Time System Specifications through Bounded Model- and Satisfiability-Checking
Abstract
In bounded model checking (BMC) a system is modeled with a finite automaton and various desired properties with temporal logic formulae. Property verification is achieved by translation into boolean logic and the application of SAT-solvers. bounded satisfiability checking (BSC) adopts a similar approach, but both the system and the properties are modeled with temporal logic formulae, without an underlying operational model. Hence, BSC supports a higher-level, descriptive approach to system specification and analysis. We compare the performance of BMC and BSC over a set of case studies, using the Zot tool to translate automata and temporal logic formulae into boolean logic. We also propose a method to check whether an operational model is a correct implementation (refinement) of a temporal logic model, and assess its effectiveness on the same set of case studies. Our experimental results show the feasibility of BSC and refinement checking, with modest performance loss w.r.t. BMC.
BibTeX
@inproceedings{Pradella-al:ASE08,
author = {Matteo Pradella and
Angelo Morzenti and
Pierluigi San Pietro},
title = {Refining {Real-Time} System Specifications through Bounded Model- and {Satisfiability-Checking}},
booktitle = {ASE},
pages = {119--127},
publisher = {{IEEE} Computer Society},
year = {2008},
}