CAV 1999
43 papers
- A Complete Finite Prefix for Process Algebra
- A Theory of Restrictions for Logics and Automata
- A Toolbox for the Analysis of Discrete Event Dynamic Systems
- Abstract and Model Check While You Prove
- Alternative Approaches to Hardware Verification (abstract)
- Assume-Guarantee Refinement Between Different Time Scales
- Automated Verification of a Parametric Real-Time Program: The ABR Conformance Protocol
- Automatic Verification of Abstract State Machines
- Automatic Verification of Combinatorial and Pipelined FFT
- Deciding Equality Formulas by Small Domains Instantiations
- Efficient Analysis of Cyclic Definitions
- Efficient Decision Procedures for Model Checking of Linear Time Logic Properties
- Efficient Timed Reachability Analysis Using Clock Difference Diagrams
- Elementary Microarchitecture Algebra
- Experience with Predicate Abstraction
- Exploiting Positive Equality in a Logic of Equality with Uninterpreted Functions
- Formal Methods for Conformance Testing: Theory Can Be Practical
- Handling Global Conditions in Parameterized System Verification
- Improved Automata Generation for Linear Temporal Logic
- Java Bytecode Verification by Model Checking
- Latency Insensitive Protocols
- Linking Theorem Proving and Model-Checking with Well-Founded Bisimulation
- Mechanizing Proofs of Computation Equivalence
- Model Checking Based on Sequential ATPG
- Model Checking Partial State Spaces with 3-Valued Temporal Logics
- Model Checking of Safety Properties
- Model Checking the IBM Gigahertz Processor: An Abstraction Algorithm for High-Performance Netlists
- NUSMV: A New Symbolic Model Verifier
- On the Representation of Probabilities over Structured Domains
- Optimizing Symbolic Model Checking for Constraint-Rich Models
- PIL/SETHEO: A Tool for the Automatic Analysis of Authentication Protocols
- Stepwise CTL Model Checking of State/Event Systems
- Stutter-Invariant Languages, omega-Automata, and Temporal Logic
- TIPPtool: Compositional Specification and Analysis of Markovian Performance Models
- Test Generation Derived from Model-Checking
- The Compositional Specification of Timed Systems - A Tutorial
- The Mathematical Foundation fo Symbolic Trajectory Evaluation
- Timed Automata
- Validation of Pipelined Processor Designs Using Esterel Tools: A Case Study
- Verification of Infinite-State Systems by Combining Abstraction and Reachability Analysis
- Verification of Parameterized Systems by Dynamic Induction on Diagrams
- Verifiying Safety Properties of a Power PC Microprocessor Using Symbolic Model Checking without BDDs
- Verifying Sequential Consistency on Shared-Memory Multiprocessor Systems