CGO 2004
25 papers
- A Compiler Scheme for Reusing Intermediate Computation Results
- A Dynamically Tuned Sorting Library
- Code Generation for Single-Dimension Software Pipelining of Multi-Dimensional Loops
- Compiler Optimization of Memory-Resident Value Communication Between Speculative Threads
- Custom Data Layout for Memory Parallelism
- Exploring Code Cache Eviction Granularities in Dynamic Optimization Systems
- Exploring the Performance Potential of Itanium® Processors with ILP-based Scheduling
- Exposing Memory Access Regularities Using Object-Relative Memory Profiling
- Extending Path Profiling across Loop Backedges and Procedure Boundaries
- FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths
- Improving 64-Bit Java IPF Performance by Compressing Heap References
- Ispike: A Post-link Optimizer for the Intel®Itanium®Architecture
- LLVM: A Compilation Framework for Lifelong Program Analysis & Transformation
- Optimizing Translation Out of SSA Using Renaming Constraints
- Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors
- Probabilistic Predicate-Aware Modulo Scheduling
- SYZYGY - A Framework for Scalable Cross-Module IPO
- Single-Dimension Software Pipelining for Multi-Dimensional Loops
- Software-Controlled Operand-Gating
- Specialized Dynamic Optimizations for High-Performance Energy-Efficient Microarchitecture
- Static Identification of Delinquent Loads
- Targeted Path Profiling: Lower Overhead Path Profiling for Staged Dynamic Optimization Systems
- The Accuracy of Initial Prediction in Two-Phase Dynamic Binary Translators
- Using Dynamic Binary Translation to Fuse Dependent Instructions
- VHC: Quickly Building an Optimizer for Complex Embedded Architectures