All-window profiling of concurrent executions
This paper first demonstrates the need for all-window profiling in a concurrent execution, then presents an approximate algorithm, and finally discusses related work.
1,184 papers · page 45 of 60
Matrix product on heterogeneous master-worker platforms
This paper is focused on designing efficient parallel matrix-product algorithms for heterogeneous master-worker platforms. While matrix-product is well-understood for homogeneous 2D-arrays of processors (e.g., Cannon algorithm and ScaLAPACK outer product algorithm), there are thr…
Dynamic performance tuning of word-based software transactional memory
The current generation of software transactional memories has the advantage of being simple and efficient. Nevertheless, there are several parameters that affect the performance of a transactional memory, for example the locality of the application and the cache line size of the …
Massive parallel LDPC decoding on GPU
Low-Density Parity-Check (LDPC) codes are powerful error correcting codes (ECC). They have recently been adopted by several data communication standards such as DVB-S2 and WiMax. LDPCs are represented by bipartite graphs, also called Tanner graphs, and their decoding demands very…
FastForward for efficient pipeline parallelism: a cache-optimized concurrent lock-free queue
Low overhead core-to-core communication is critical for efficient pipeline-parallel software applications. This paper presents FastForward, a cache-optimized single-producer/single-consumer concurrent lock-free queue for pipeline parallelism on multicore architectures, with weak …
Design and implementation of a high-performance MPI for C# and the common language infrastructure
As high-performance computing enters the mainstream, parallel programming mechanisms (including the Message Passing Interface, or MPI) must be supported in new environments such as C# and the Common Language Infrastructure (CLI). Making effective use of MPI with the CLI requires …
On the correctness of transactional memory
Transactional memory (TM) is perceived as an appealing alternative to critical sections for general purpose concurrent programming. Despite the large amount of recent work on TM implementations, however, very little effort has been devoted to precisely defining what guarantees th…
Programming with tiles
The importance of tiles or blocks in scientific computing cannot be overstated. Many algorithms, both iterative and recursive, can be expressed naturally if tiles are represented explicitly. From the point of view of performance, tiling, either as a code or a data layout transfor…
Transactional boosting: a methodology for highly-concurrent transactional objects
We describe a methodology for transforming a large class of highly-concurrent linearizable objects into highly-concurrent transactional objects. As long as the linearizable implementation satisfies certain regularity properties (informally, that every method has an inverse), we d…
A portable runtime interface for multi-level memory hierarchies
We present a platform independent runtime interface for moving data and computation through parallel machines with multi-level memory hierarchies. We show that this interface can be used as a compiler target and can be implemented easily and efficiently on a variety of platforms.…
ZOID: I/O-forwarding infrastructure for petascale architectures
The ZeptoOS project is developing an open-source alternative to the proprietary software stacks available on contemporary massively parallel architectures. The aim is to enable computer science research on these architectures, enhance community collaboration, and foster innovatio…
Cache-aware iteration space partitioning
The need for high performance per watt has led to the development of multi-core systems such as the Intel Core 2 Duo processor and the Intel quad-core Kentsfield processor. Maximal exploitation of the hardware parallelism supported by such systems necessitates the development of …
Split hardware transactions: true nesting of transactions using best-effort hardware transactional memory
Transactional Memory (TM) is on its way to becoming the programming API of choice for writing correct, concurrent, and scalable programs. Hardware TM (HTM) implementations are expected to be significantly faster than pure software TM (STM); however, full hardware support for true…
Formal specification of the MPI-2.0 standard in TLA+
No abstract available.
Toward high performance nonblocking software transactional memory
Substantial advances in STM performance in recent years have mostly focused on blocking systems. We describe our work integrating the most important techniques and optimizations emerging from the recent work on blocking STMs into several variants of a nonblocking STM.
Concurrent GC leveraging transactional memory
We predict that the ever-growing number of cores on our desktops will require a re-examination of concurrent programming. Two technologies are likely to become mainstream in response: Transactional memory provides a superior programming model to traditional lock-based concurrency…
Where will all the threads come from?
Today, multicore microprocessors are at the heart of systems ranging from laptops to supercomputers. The shift to multicore architectures has transformed the problem of improving program performance from a micro-architecture problem to a software problem, shifting the focus from …
Quasi-static scheduling for safe futures
Migrating sequential programs to effectively utilize next generation multicore architectures is a key challenge facing application developers and implementors. Languages like Java that support complex control- and dataflow abstractions confound classical automatic parallelization…
Performance without pain = productivity: data layout and collective communication in UPC
The next generations of supercomputers are projected to have hundreds of thousands of processors. However, as the numbers of processors grow, the scalability of applications will be the dominant challenge. This forces us to reexamine some of our fundamental ways that we approach …
Probabilistic advanced reservations for batch-scheduled parallel machines
No abstract available.