Optimizing Static Power Dissipation by Functional Units in Superscalar Processors
No abstract available.
Related papers
- Scalar Interpolation: A Better Balance between Vector and Scalar Execution for SuperScalar Architectures CGO 2025
- VLIW Compilation Techniques in a Superscalar Environment PLDI 1994
- VHC: Quickly Building an Optimizer for Complex Embedded Architectures CGO 2004
- Global Variable Promotion: Using Registers to Reduce Cache Power Dissipation CC 2002
- Constructing Virtual Architectures on a Tiled Processor CGO 2006
- Dynamic compilation of data-parallel kernels for vector processors CGO 2012
- Link-time optimization for power efficiency in a tagless instruction cache CGO 2011
- Global Instruction Scheduling for Superscalar Machines PLDI 1991