Checking Safety Properties of Behavioral VHDL Descriptions by Abstract Interpretation
Abstract elided by the publisher.
Related papers
- A Refinement Calculus for the Synthesis of Verified Hardware Descriptions in VHDL TOPLAS 1997
- A VHDL Compiler Based on Attribute Grammar Methodology PLDI 1989
- Abstract Interpretation-Based Static Analysis of Mobile Ambients SAS 2001
- An abstract interpretation framework for termination POPL 2012
- Verification of timing Properties of VHDL CAV 1993
- Automatic Completion of Distributed Protocols with Symmetry CAV 2015
- Abstract Interpretation of Temporal Safety Effects of Higher Order Programs OOPSLA 2025
- Goblint: Abstract Interpretation for Memory Safety and Termination - (Competition Contribution) TACAS 2024