CAV 1997
52 papers
- A Compositional Rule for Hardware Design Refinement
- A Provably Correct Embedded Verifier for the Certification of Safety Critical Software
- An Efficient Decision Procedure for the Theory of Fixed-Sized Bit-Vectors
- An Improved Reachability Analysis Method for Strongly Linear Hybrid Systems (Extended Abstract)
- An n log n Algorithm for Online BDD Refinement
- Automatic Abstraction Techniques for Propositional µ-calculus Model Checking
- Automatic Datapath Extraction for Efficient Usage of HDD
- Boolean and 2-adic Numbers Based Techniques for Verifying Synchronous Design
- Combining Constraint Solving and Symbolic Model Checking for a Class of a Systems with Non-linear Constraints
- Construction of Abstract State Graphs with PVS
- Containing of Regular Languages in Non-Regular Timing Diagram Languages is Decidable
- Deadlock Checking Using Net Unfoldings
- Efficient Detection of Vacuity in ACTL Formulaas
- Efficient Model Checking Using Tabled Resolution
- Efficient Modeling of Memory Arrays in Symbolic Simulation
- Exploiting Symmetry When Verifying Transitor-Level Circuits by Symbolic Trajectory Evaluation
- Formal Verification - Applications & Case Studies
- Formal Verification of Digital Systems, from ASICs to HW/SW Codesign - a Pragmatic Approach
- HYTECH: A Model Checker for Hybrid Systems
- MOSEL: A Sound and Efficient Tool for M2L(Str)
- Model Checking and Transitive-Closure Logic
- Model Checking in a Microprocessor Design Project
- Module Checking Revisited
- On Combining Formal and Informal Verification
- On-the-Fly Model Checking Under Fairness That Exploits Symmetry
- Parallelizing the Murphi Verifier
- Parametrized Verification of Linear Networks Using Automata as Invariants
- Partial-Order Reduction in Symbolic State Space Exploration
- Practical Challenges for Industrial Formal Verification Tools
- Programs with Quasi-Stable Channels are Effectively Recognizable (Extended Abstract)
- Relaxed Visibility Enhances Partial Order Reduction
- RuleBase: Model Checking at IBM
- SMC: A Symmetry Based Model Checker for Verification of Liveness Properties
- STARI: A Case Study in Compositional and Hierarchical Timing Verification
- Some Progress in the Symbolic Verification of Timed Automata
- Some Thoughts on Statecharts, 13 Years Later
- Symbolic Model Checking of Infinite State Systems Using Presburger Arithmetic
- Symbolic Model Checking with Rich ssertional Languages
- TermiLog: A System for Checking Termination of Queries to Logic Programs
- The Industrial Success of Verification Tools Based on Stålmarck's Method
- The Invariant Checker: Automated Deductive Verification of Reactive Systems
- The PEP Tool
- The Verus Tool: A Quantitative Approach to the Formal Verification of Real-Time Systems
- Towards a Mechanization of Cryptographic Protocal Verification
- Trace Table Based Approach for Pipeline Microprocessor Verification
- UPPAAL: Status & Developments
- Using Compositional Preorders in the Verification of Sliding Window Protocal
- VeriSoft: A Tool for the Automatic Analysis of Concurrent Reactive Software
- Verification of a Chemical Process Leak Test Procedure
- Weak Bisimulation for Fully Probabilistic Processes
- prod 3.2: An Advanced Tool for Efficient Reachability Analysis
- µcke - Efficient µ-Calculus Model Checking