Enhancing the performance of MPI-IO applications by overlapping I/O, computation and communication
No abstract available.
1,184 papers · page 46 of 60
Modeling optimistic concurrency using quantitative dependence analysis
This work presents a quantitative approach to analyze parallelization opportunities in programs with irregular memory access where potential data dependencies mask available parallelism. The model captures data and causal dependencies among critical sections as algorithmic proper…
Extracting coarse-grain parallelism in general-purpose programs
While the chip multiprocessor (CMP) has quickly become the predominant processor architecture, its continuing success largely depends on the parallelizability of complex programs. In the early 1990s great successes were obtained to extract parallelism from the inner loops of scie…
Optimization principles and application performance evaluation of a multithreaded GPU using CUDA
GPUs have recently attracted the attention of many application developers as commodity data-parallel coprocessors. The newest generations of GPU architecture provide easier programmability and increased generality while maintaining the tremendous memory bandwidth and computationa…
Assertional reasoning about data races in relaxed memory models
We describe the ideas behind a method to use assertional reasoning to statically show that all sequentially consistent executions of a concurrent program are free from data races.
Experience on optimizing irregular computation for memory hierarchy in manycore architecture
No abstract available.
An adaptive memory conscious approach for mining frequent trees: implications for multi-core architectures
We consider the problem of frequent tree mining and present algorithms targeting emerging single-chip multiprocessor (CMP) architectures. We explore algorithmic designs that improve the memory performance of such algorithms, both in terms of alleviating latency to memory as well …
ISP: a tool for model checking MPI programs
No abstract available.
Automated application-level checkpointing based on live-variable analysis in MPI programs
This paper proposes an optimization method of data saving for application-level checkpointing based on the live-variable analysis method for MPI programs. We presents the implementation of a source-to-source precompiler (CAC) for automating applicationlevel checkpointing based on…
Compiler optimizations for parallelizing general-purpose applications under thread-level speculation
No abstract available.
Potential show-stoppers for transactional synchronization
No abstract available.
Transactional programming in a multi-core environment
With single thread performance starting to plateau, HW architects have turned to chip level multiprocessing (CMP) to increase processing power. All major microprocessor companies are aggressively shipping multi-core products in the mainstream computing market. Moore's law will la…
May-happen-in-parallel analysis of X10 programs
X10 is a modern object-oriented programming language designed for high performance, high productivity programming of parallel and multi-core computer systems. Compared to the lower-level thread-based concurrency model in the JavaTM language, X10 has higher-level concurrency const…
Adaptive work stealing with parallelism feedback
We present an adaptive work-stealing thread scheduler, A-Steal, for fork-join multithreaded jobs, like those written using the Cilk multithreaded language or the Hood work-stealing library. The A-Steal algorithm is appropriate for large parallel servers where many jobs share a co…
Performance evaluation of the cray XT3 configured with dual core opteron processors
No abstract available.
Promised messages: recovering from inconsistent global states
No abstract available.
Dynamic multigrain parallelization on the cell broadband engine
This paper addresses the problem of orchestrating and scheduling parallelism at multiple levels of granularity on heterogeneous multicore processors. We present mechanisms and policies for adaptive exploitation and scheduling of layered parallelism on the Cell Broadband Engine. O…
Reordering constraints for pthread-style locks
C or C++ programs relying on the pthreads interface for concurrency are required to use a specified set of functions to avoid data races, and to ensure memory visibility across threads. Although the detailed rules are not completely, it is not hard to refine them to a simple set …
Automatic mapping of nested loops to FPGAS
This paper present a framework for automatic mapping of perfectly nested loops with constant dependences onto regular processor arrays, suitable for direct implementation on Field Programmable Gate Arrays (FPGAs). The problem is modeled as that of finding a suitable completion pr…
Toward terabyte pattern mining: an architecture-conscious solution
We present a strategy for mining frequent item sets from terabyte-scale data sets on cluster systems. The algorithm embraces the holistic notion of architecture-conscious datamining, taking into account the capabilities of the processor, the memory hierarchy and the available net…