The PEP Tool
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On-the-Fly Model Checking Under Fairness That Exploits Symmetry
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Some Thoughts on Statecharts, 13 Years Later
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HYTECH: A Model Checker for Hybrid Systems
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Formal Verification of Digital Systems, from ASICs to HW/SW Codesign - a Pragmatic Approach
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Model Checking and Transitive-Closure Logic
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Using Compositional Preorders in the Verification of Sliding Window Protocal
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Automatic Datapath Extraction for Efficient Usage of HDD
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MOSEL: A Sound and Efficient Tool for M2L(Str)
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Symbolic Model Checking with Rich ssertional Languages
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An n log n Algorithm for Online BDD Refinement
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Relaxed Visibility Enhances Partial Order Reduction
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Module Checking Revisited
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UPPAAL: Status & Developments
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TermiLog: A System for Checking Termination of Queries to Logic Programs
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Practical Challenges for Industrial Formal Verification Tools
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A Compositional Rule for Hardware Design Refinement
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Deadlock Checking Using Net Unfoldings
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Exploiting Symmetry When Verifying Transitor-Level Circuits by Symbolic Trajectory Evaluation
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Automatic Abstraction Techniques for Propositional µ-calculus Model Checking
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