Exploiting Symmetry In Temporal Logic Model Checking
Abstract elided by the publisher.
2,069 papers · page 97 of 104
Verification of timing Properties of VHDL
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Generation of Reduced Models for Checking Fragments of CTL
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On Model-Checking for Fragments of µ-Calculus
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Symmetry and Model Checking
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Symbolic Equivalence Checking
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Refining Dependencies Improves Partial-Order Verification Methods (Extended Abstract)
Abstract elided by the publisher.
A Verifier and Timing Analyser for Simple Imperative Programs (Abstract)
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A Tool for Symbolic Program Verification and Abstration
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Parametric Circuit Representation Using Inductive Boolean Functions
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Delay Analysis in Synchronous Programs
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A Modal Logic for Message passing Processes (Extended Abstract)
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BDD-Based Debugging Of Design Using Language Containment and Fair CTL
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Efficient Verification with BDDs using Implicitly Conjoined Invariants
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Combining Model Checking and Theorem Proving to Verify Parallel Processes
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Verifying Quantitative Real-Time Properties of Synchronous Programs
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A Decision Algorithm for Full Propositional Temporal Logic
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Reachability and Recurrence in Extended Finite State Machines: Modular Vector Addition Systems
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Verification of a Multiplier: 64 Bits and Beyond
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A Structural Linearization Principle for Processes
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