CAV 1993
40 papers
- A Decision Algorithm for Full Propositional Temporal Logic
- A Graphical Interval Logic Toolset for Verifying Concurrent Systems
- A Mechanically Verified Application for a Mechanically Verified Environment
- A Modal Logic for Message passing Processes (Extended Abstract)
- A Structural Linearization Principle for Processes
- A Tool for Symbolic Program Verification and Abstration
- A Verifier and Timing Analyser for Simple Imperative Programs (Abstract)
- All from One, One for All: on Model Checking Using Representatives
- Alternating RQ Timed Automata
- An Efficient Algorithm for Minimizing Real-time Transition Systems
- An Iterative Approach to Language Containment
- Automatic Generation of Network Invariants for the Verification of Iterative Sequential Systems
- BDD-Based Debugging Of Design Using Language Containment and Fair CTL
- Combining Model Checking and Theorem Proving to Verify Parallel Processes
- Computer-Assisted Simulation Proofs
- Computing Accumulated Delays in Real-time Systems
- Delay Analysis in Synchronous Programs
- Efficient Verification of Parallel Real-Time Systems
- Efficient Verification with BDDs using Implicitly Conjoined Invariants
- Exploiting Symmetry In Temporal Logic Model Checking
- Functionality Decomposition by Compositional Correstness Preserving Transformation
- Generation of Reduced Models for Checking Fragments of CTL
- Logic Synthesis and Design Verification
- On Model-Checking for Fragments of µ-Calculus
- On-the-Fly Verification with Stubborn Sets
- Parametric Circuit Representation Using Inductive Boolean Functions
- Protocol Design for an Automated Highway System (Abstract)
- Reachability Analysis of Planar Multi-limear Systems
- Reachability and Recurrence in Extended Finite State Machines: Modular Vector Addition Systems
- Refining Dependencies Improves Partial-Order Verification Methods (Extended Abstract)
- Reliable Hashing without Collosion Detection
- Symbolic Equivalence Checking
- Symmetry and Model Checking
- The Formal Verification of an Algorithm for Interactive Consistency under a Hybrid Fault Model
- Timed Modal Specification - Theory and Tools
- Verification of Real-Time Systems Using PVS
- Verification of a Multiplier: 64 Bits and Beyond
- Verification of timing Properties of VHDL
- Verifying Quantitative Real-Time Properties of Synchronous Programs
- Verifying Timed Behavior Automata with Input/Output Critical Races